In 2022, the PCI-SIG developer conference is being held in full swing, and the standards committee PCI-SIG, which hides behind the ubiquitous PCIe interface standard, announced that the goal of PCIe 7.0 specification is to release it to its members in 2025, with a data rate of up to 128 GT/s. Before encoding overhead, this is equivalent to 512 GB/s bidirectional throughput over 16 channel (x16) connections. PCI-SIG is the alliance behind PCIe interface, which is an open industry standard composed of more than 900 member companies.

PCI-SIG pointed out that PCIe 7.0 interface will provide bidirectional throughput up to 512 GB/s through x16 connection, but this is before the impact of encoding overhead and header efficiency, both of which will affect the available bandwidth.

PCIe 7.0 interface will continue to use 1b/1b flit mode coding and PAM4 signal technology introduced with PCIe 6.0, which is significantly improved compared with 128b/130b coding and NRZ signal used in PCIe 3.0 to PCIe 5.0 specifications. Therefore, the actual available bandwidth will be slightly less than 512 GB/s, but still represents twice the PCIe 6.0 interface.

As we saw when jumping to PCIe 4.0 and 5.0, the length of PCIe cabling will be shortened again due to the faster signal transmission rate. This means that the minimum allowable distance between the PCIe root device (such as CPU) and the terminal device (such as GPU) will be shortened without additional components. Therefore, compared with what we have seen in previous generations of interfaces, the motherboard will require more retimers and thicker PCBs made of higher quality materials, and PCIe 7.0 support will lead to another increase in motherboard prices.

It is worth noting that the bandwidth of each channel will be higher. Now the two-way bandwidth of x1 connection is 32 GB/s, allowing "thinner" connection of some devices (for example, using x4 instead of x8 connection).

The basic work of the PCIe 7.0 specification was formulated after PCI-SIG completed the PCIe 6.0 specification earlier this year. It will provide twice the bandwidth of the previous generation PCIe 6.0 interface. However, it will take us a while to see devices such as SSDs and GPUs that support this fast interface - these specifications are usually approved and finalized long before we see silicon wafers shipped.

You will notice that there are still not many PCIe 5.0 devices in the market, although this interface does appear on the mainstream motherboards of Intel Alder Lake, and will also appear on the platforms that will arrive later this year on the upcoming Zen 4 Ryzen 7000 of AMD. The first PCIe 5.0 SSDs will be available at the same time as the Ryzen 7000 processor, but we have seen the product announcements of PCIe 5.0 devices for data centers and AI/ML devices.

In other words, you will not see PCIe 7.0 devices in the market for a long time, although PCI-SIG is now beginning to define specifications and hopes to achieve its goal of releasing a new specification every three years. The PCIe 7.0 specification is expected to be implemented in 2025, but we will not see the terminal equipment until 2028.

PCIe 7.0 specification objectives:

128 GT/s raw bit rate and 512 GB/s bidirectional transmission rate through x16 configuration

Using PAM4 (4-stage pulse amplitude modulation) signaling

Focus on channel parameters and coverage

Continue to deliver low latency and high reliability

Improve power efficiency

Maintain backward compatibility with all previous generation PCIe technologies

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"For 30 years, the guiding principle of PCI-SIG has been, 'If we build it, they will come,'" said Nathan Brookwood, a researcher at Insight 64. "The early parallel version of PCI technology can accommodate hundreds of megabytes/second, matching the graphics, storage and network needs of the 1990s. In 2003, PCI-SIG evolved into a serial design that supports gigabytes/second speed to adapt to faster solid-state disks and 100MbE Ethernet. Almost like clockwork, PCI-SIG doubled the PCIe specification bandwidth every three years to meet the challenges of emerging applications and markets. Today, PCI-SIG announced The plan is to double the channel speed to 512 GB/s (bidirectional), which is expected to double the PCIe specification performance in another three-year cycle. " He further pointed out.

"With the upcoming PCIe 7.0 specification, PCI-SIG continues our 30-year commitment to provide industry-leading specifications that drive innovation boundaries," said Al Yanes, president and chairman of PCI-SIG. "As PCIe technology continues to evolve to meet high bandwidth requirements, our team will focus on channel parameters and coverage, as well as improving power efficiency." Al Yanes continued.

The PCIe 7.0 specification is designed to support emerging applications, such as 800 G Ethernet, AI/ML, cloud and quantum computing; And data intensive markets, such as ultra large scale data centers, high-performance computing (HPC), and military/aerospace.